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november 2012 ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan2108 ? rev. 1.0.2 fan2108 ? tinybuck?, 3-24 v input, 8 a, high-e fficiency, integrated synchronous buck regulator fan2108 ? tinybuck? 3-24 v input, 8 a, high-efficiency, integrated synchronous buck regulator features ? wide input voltage range: 3 v-24 v ? wide output voltage range: 0.8 v to 80% v in ? 8 a output current ? programmable frequency operation: 200 khz to 600 khz ? over 95% peak efficiency ? integrated schottky diode on low-side mosfet boosts efficiency ? internal bootstrap diode ? power-good signal ? pre-bias startup ? accepts ceramic capacitors on output ? external compensation for flexible design ? input under-voltage lockout ? programmable current limit ? under-voltage, over-voltage, and thermal shutdown protections ? internal soft-start ? 5x6mm, 25-pin, 3-pad mlp package applications ? servers ? point-of-load regulation ? high-end computing systems ? graphics cards ? battery-powered equipment ? set-top boxes description the fan2108 tinybuck? is a highly efficient, small footprint, 8 a, synchronous buck regulator. the fan2108 contains both synchronous mosfets and a controller/driver with optimized interconnects in one package, which enables designers to solve high- current requirements in a small area with minimal external components. external compensation, programmable switching frequency, and current limit features allow design optimization and flexibility. the summing current mode modulator uses lossless current sensing for current feedback and over-current protection. voltage feedforward helps operation over a wide input voltage range. fairchild?s advanced bicmos power process, combined with low-r ds(on) internal mosfets and a thermally efficient mlp package, prov ide the ability to dissipate high power in a small package. output over-voltage, under-voltage, and thermal shutdown protections help protect the device from damage during fault conditions. fan2108 prevents pre-biased output discharge dur ing startup in point-of- load applications. related application notes an-8022 ? tinycalc? calculator ordering information part number operating temperature range package packing method fan2108mpx -10c to 85c molded leadless package (mlp) 5x6 mm tape and reel fan2108empx -40c to 85c molded leadless package (mlp) 5x6 mm tape and reel
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan2108 ? rev. 1.0.2 2 fan2108 ? tinybuck?, 3-24 v input, 8 a, high-efficiency , integrated synchronous buck regulator typical application q1 q2 sw fb p1 pgnd p3 c out out l p2 boot 1 comp vcc r2 pgood en +5v c1 agnd r1 ramp 20 15 25 13 14 19 16 18 r(t) r t 17 ilim r ilim 24 pwm + driver c boot r3 c3 r bias r ramp c2 in c in c hf c4 power good enable boot diode power mosfets nc figure 1. typical application diagram block diagram figure 2. block diagram
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan2108 ? rev. 1.0.2 3 fan2108 ? tinybuck?, 3-24 v input, 8 a, high-efficiency , integrated synchronous buck regulator pin configuration figure 3. mlp 5x6 mm pin configuration (bottom view) pin definitions pin # name description p1, 6-12 sw switching node . p2, 2-5 vin power input voltage . connect to the main input power source. p3, 21-23 pgnd power ground . power return and q2 source. 1 boot high-side drive boot voltage . connect through capacitor (c boot ) to sw. the ic includes an internal synchronous bootstrap diode to re charge the capacitor on this pin to v cc when sw is low. 13 pgood power-good flag . an open-drain output that pulls lo w when fb is outside a 10% range of the reference. pgood does not assert high until the fault latch is enabled. 14 en enable . enables operation when pulled to logic high or left open. toggling en resets the regulator after a latched fault condition. this input has an internal pull-up when the ic is functioning normally. when a latched fault occurs, en is discharged by a current sink. 15 vcc input bias supply for ic . the ic?s logic and analog circuitry are powered from this pin. 16 agnd analog ground . the signal ground for the ic. all internal control voltages are referred to this pin. tie this pin to the ground isl and/plane through the lowe st impedance connection. 17 ilim current limit . a resistor (r ilim ) from this pin to agnd can be used to program the current- limit trip threshold lower than the default setting. 18 r(t) oscillator frequency . a resistor (r t ) from this pin to agnd sets the pwm switching frequency. 19 fb output voltage feedback . connect through a resistor di vider to the output voltage. 20 comp compensation . error amplifier output. connect the ex ternal compensation network between this pin and fb. 24 nc no connect . this pin is not used. 25 ramp ramp amplitude . a resistor (r ramp ) connected from this pin to v in sets the ramp amplitude and provides voltage feedfor ward functionality.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan2108 ? rev. 1.0.2 4 fan2108 ? tinybuck?, 3-24 v input, 8 a, high-efficiency , integrated synchronous buck regulator absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. parameter conditions min. max. unit vin to pgnd 28 v vcc to agnd agnd=pgnd 6 v boot to pgnd 35 v boot to sw -0.3 6.0 v sw to pgnd continuous -0.5 24.0 v transient (t < 20 ns, f < 600 khz) -5 30 v all other pins -0.3 v cc +0.3 v esd human body model, jedec jesd22-a114 2 kv charged device model, jedec jesd22-c101 2.5 recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. typ. max. unit v cc bias voltage vcc to agnd 4.5 5.0 5.5 v v in supply voltage vin to pgnd 3 24 v t a ambient temperature fan2108mpx -10 +85 c fan2108empx -40 +85 c t j junction temperature +125 c f switching frequency 600 khz thermal information symbol parameter min. typ. max. unit t stg storage temperature -65 +150 c t l lead soldering temperature, 10 seconds +300 c t vp vapor phase, 60 seconds +215 c t i infrared, 15 seconds +220 c jc thermal resistance: junction-to-case p1 (q2) 4 c/w p2 (q1) 7 c/w p3 4 c/w j-pcb thermal resistance: junc tion-to-mounting surface (1) 35 c/w p d power dissipation, t a =25c (1) 2.8 w note: 1. typical thermal resistance when mount ed on a four-layer, two-ounce pcb, as shown in figure 25. actual results are dependent on mounting method and surf ace related to the design.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan2108 ? rev. 1.0.2 5 fan2108 ? tinybuck?, 3-24 v input, 8 a, high-efficiency , integrated synchronous buck regulator electrical specifications electrical specifications are the result of using the circuit shown in figure 1 unless otherwise noted. symbol parameter conditions min. typ. max. unit power supplies i cc v cc current sw=open, fb=0.7 v, v cc =5 v, f sw =600 khz 8 12 ma shutdown: en=0, v cc =5 v 7 10 a v uvlo v cc uvlo threshold rising v cc 4.1 4.3 4.5 v hysteresis 300 mv oscillator f frequency r t =50 k 255 300 345 khz r t =24 k 540 600 660 khz t on minimum on-time (2) 50 65 ns v ramp ramp amplitude, peak-to?peak 16 v in , 1.8 v out , r t =30 k , r ramp =200 k 0.53 v t off minimum off-time (2) 100 150 ns reference v fb reference voltage (see figure 4 for temperature coefficient) fan2108mpx, 25c 794 800 806 mv fan2108empx, 25c 795 800 805 mv error amplifier g dc gain (2) v cc =5 v 80 85 db bw gain bandwidth product (2) 12 15 mhz v comp output voltage 0.4 3.2 v i sink output current, sourcing v cc =5 v, v comp =2.2 v 1.5 2.2 ma i source output current, sinking v cc =5 v, v comp =1.2 v 0.8 1.2 ma i bias fb bias current v fb =0.8 v, 25c -850 -650 -450 na protection and shutdown i lim current limit r ilim open at 25c (see circuit description) 12 15 18 a i ilim i lim current -11 -10 -9 a t tsd over-temperature shutdown internal ic temperature +155 c t hys over-temperature hysteresis +30 c v ovp over-voltage threshold two c onsecutive clock cycles 110 115 121 %v out v uvlo under-voltage shutdown 16 cons ecutive clock cycles 68 73 78 %v out v flt fault discharge threshold measured at fb pin 250 mv v flt_hys fault discharge hysteresis measured at fb pin (v fb ~500 mv) 250 mv soft-start t ss v out to regulation (t0.8) frequency=600 khz 5.3 ms t en fault enable/ssok (t1.0) 6.7 ms note: 2. specifications guaranteed by design and characteri zation; not production tested.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan2108 ? rev. 1.0.2 6 fan2108 ? tinybuck?, 3-24 v input, 8 a, high-efficiency , integrated synchronous buck regulator electrical specifications (continued) recommended operating conditions are the result of using the circuit show n in figure 1 unless otherwise noted. symbol parameter conditions min. typ. max. unit control functions v en_r en threshold, rising 1.35 2.00 v v en_hys en hysteresis 250 mv r en en pull-up resistance 800 k i en en discharge current auto-restart mode 1 a r fb fb ok drive resistance 800 v pg pgood threshold fb < v ref -14 -11 -8 %v ref fb > v ref +7 +10 +13.5 v pg_l pgood output low i out < 2 ma 0.4 v
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan2108 ? rev. 1.0.2 7 fan2108 ? tinybuck?, 3-24 v input, 8 a, high-efficiency , integrated synchronous buck regulator typical characteristics 0.990 0.995 1.000 1.005 1.010 -50 0 50 100 150 temperature ( o c) v fb 0.80 0.90 1.00 1.10 1.20 -50 0 50 100 150 temperature ( o c) i fb figure 4. reference voltage (v fb ) vs. temperature, normalized figure 5. reference bias current (i fb ) vs. temperature, normalized 0 300 600 900 1200 1500 0 20 40 60 80 100 120 140 r t (k ) frequency (khz ) 0.98 0.99 1.00 1.01 1.02 -50 0 50 100 150 temperature ( o c) frequency figure 6. frequency vs. r t figure 7. frequency vs. temperature, normalized 0.6 0.8 1 1.2 1.4 -50 0 50 100 150 tem p erature ( c ) r ds 0.96 0.98 1.00 1.02 1.04 -50 0 50 100 150 temperature ( o c) i ilim figure 8. r ds vs. temperature, normalized (v cc =v gs =5v) figure 9. i lim current (i ilim ) vs. temperature, normalized 300khz 600khz q1 ~0.32%/c q2 ~0.35%/c
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan2108 ? rev. 1.0.2 8 fan2108 ? tinybuck?, 3-24 v input, 8 a, high-efficiency , integrated synchronous buck regulator application circuit sw p1 pgnd p3 v out p2 vin boot 1 comp vcc pgood 8-20 v in en +5v agnd ramp 20 15 25 13 14 16 18 r(t) 17 ilim 24 19 fb v out 3 x 4.7u * inter-technical sc7232-2r2m 390p 1.5 4 x 22u 3.3n 200k 200k 2.00k 30.1k 3.3n 1.0u 10k 2.49k 2.49k 56p 4.7n 62 4.7n 0.1u 2.2u * x5r x7r x5r nc figure 10. application circuit: 1.8 v out , 500 khz typical performance characteristics typical operating characteristics usi ng the circuit shown in figure 10. v in =12 v, v cc =5 v, unless otherwise specified. efficiency @ vo=1.8v, fsw=500khz, ta=25 0 c 70 75 80 85 90 95 02468 load current (a) efficiency (%) vin=8v vin=12v vin=16v vin=20v vin=24v efficiency @ vo=3.3v, fsw=300khz, ta=25 0 c 70 75 80 85 90 95 100 02468 load current (a) efficiency (%) vin=5v vin=10v vin=12v vin=14v vin=20v figure 11. 1.8 v out efficiency over v in vs. load figure 12. 3.3 v out efficiency over v in vs. load efficiency@ vin=12v, vo=1.8v 70 75 80 85 90 95 012345678 load current (a) efficiency (%) 300khz 500khz 600khz load regulation @ vo=0.8v, 500khz, 25c 0.7992 0.7994 0.7996 0.7998 0.8 0.8002 0.8004 0.8006 0.8008 0.801 0.8012 012345678 load current (a) output voltage (v) vin=8v vin=12v vin=16v vin=20v vin=24v figure 13. 1.8 v out efficiency over frequency vs. load figure 14. 0.8 v out load regulation over v in vs. load typical performance characteristics (continued)
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan2108 ? rev. 1.0.2 9 fan2108 ? tinybuck?, 3-24 v input, 8 a, high-efficiency , integrated synchronous buck regulator typical operating characteristics usi ng the circuit shown in figure 10. v in =12 v, v cc =5 v, unless otherwise specified. figure 15. startup, 3 a load figure 16. startup with 1 v pre-bias on v out figure 17. shutdown, 1 a load figure 18. restart on fault hs and ls mosfet temperature 20 30 40 50 60 70 80 90 02468 load current (a) temperature ( c) lsfet@ 20vin lsfet@ 12vin hsfet@ 20vin hsfet@ 12vin figure 19. transient response, 2-8 a load figure 20. mosfet temperature ? still air at room temperature v out pgood en v out sw en v out pgood en sw en v out i out
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan2108 ? rev. 1.0.2 10 fan2108 ? tinybuck?, 3-24 v input, 8 a, high-efficiency , integrated synchronous buck regulator circuit description initialization once v cc exceeds the uvlo threshold and en is high, the ic checks for an open or shorted fb pin before releasing the internal soft-start ramp (ss). if r1 is open (figure 1) , the error amplifier output (comp) is forced low and no pulses are generated. after the ss ramp times out (t1.0), an under-voltage latched fault occurs. if the parallel combination of r1 and r bias is 1 k , the internal ss ramp is not re leased and the regulator does not start. bias supply the fan2108 requires a 5 v supply rail to bias the ic and provide gate-drive energy. connect a 1.0 f x5r or x7r decoupling capacit or between vcc and pgnd. since v cc is used to drive the internal mosfet gates, supply current is frequency and voltage dependent. approximate v cc current (i cc ) is calculated by: )] 128 ( ) 013 . 0 227 5 [( 58 . 4 ) ( ? ? + ? + = f v i cc ma cc (1 ) where frequency (f) is expressed in khz. enable fan2108 has an internal pull-up to enable pin so that the ic is enabled once v cc is applied. connecting a small capacitor across en and agnd delays the rate of voltage rise on the en pin. en pin also serves for the restart whenever a fault occurs (refer to the auto-restart section) . for applications where sequencing is required, fan2108 can be enabled (after the v cc comes up) with external control, as shown in figure 20. figure 20. enabling with external control setting the frequency oscillator frequency is determined by an external resistor, r t , connected between the r(t) pin and agnd. resistance is calculated by: 65 135 ) / 10 ( 6 ) ( ? = f r k t (2) where r t is in k and frequency (f) is in khz. the regulator cannot start if r t is left open. soft-start once internal ss ramp has charged to 0.8 v (t0.8), the output voltage is in regulation. until ss ramp reaches 1.0 v (t1.0), the fault latch is inhibited. to avoid skipping the soft-start cycle, it is necessary to apply v in before v cc reaches its uvlo threshold. soft-start time is a function of oscillator frequency. ss 1.35v fb en 0.8v t0.8 t1.0 3200 clks 4000 clks fault latc h enable 0.8v 1.0v 2400 clks figure 21. soft-start timing diagram the regulator does not allow the low-side mosfet to operate in full synchronous rectification mode until internal ss ramp reaches 95% of v ref (~0.76 v). this helps the regulator to st art on a pre-biased output and ensures that inductor current does not "ratchet" up during the soft-start cycle. v cc uvlo or toggling the en pin discharges the ss and resets the ic. setting the output voltage the output voltage of the regulator can be set from 0.8 v to 80% of v in by an external resistor divider (r1 and r bias in figure 1). the internal reference is 0.8 v with 650 na, sourced from the fb pin to ensure that, if the pin is open, the regulator does not start. the external resistor divider is calculated using: na r v v r v out bias 650 1 8 . 0 8 . 0 + ? = (3) connect r bias between fb and agnd.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan2108 ? rev. 1.0.2 11 fan2108 ? tinybuck?, 3-24 v input, 8 a, high-efficiency , integrated synchronous buck regulator calculating the inductor value typically the inductor is set for a ripple current ( i l ) of 10% to 35% of the maximum dc load. regulators requiring fast transient response use a value on the high side of this range; while regulators that require very low output ripple and/or use high-esr capacitors restrict allowable ripple current. f ) v - (1 v out out ? ? = l in i v l (4) where f is the oscillator frequency. setting the ramp resistor value the internal ramp voltage excursion ( ? v ramp ) during t on should be set to 0.6 v at nominal operating point. r ramp is approximately: 2 10 18 ) 8 . 1 ( 6 ) ( ? ? ? ? ? = ? f v x v v r in out in k ramp (5) where frequency (f) is expressed in khz. setting the current limit the current limit system involves two comparators. the max i limit comparator is used with a v ilim fixed-voltage reference and represents the maximum current limit allowable. this reference voltage is temperature compensated to reflect the r dson variation of the low- side mosfet. the adjust i limit comparator is used where the current limit needs to be set lower than the v ilim fixed reference. the 10 a current source does not track the r dson changes over temperature, so change is added into the equations for calculating the adjust i limit comparator reference voltage, as is shown below. figure 22 shows a simplified schematic of the over- current system. figure 22. current-limit system schematic since the i lim voltage is set by a 10 a current source into the r ilim resistor, the basic equation for setting the reference voltage is: v rilim = 10a*r ilim (6) to calculate r ilim : r ilim = v rilim / 10a (7) the voltage v rilim is made up of two components, v bot (which relates to the current through the low-side mosfet) and v rmpeak (which relates to the peak current through the inductor). combining those two voltage terms results in: r ilim = (v bot + v rmpeak )/ 10a (8) r ilim = {0.96 + (i load * r dson *k t *8)} + {d*(v in ? 1.8)/(f sw *0.03*r ramp )}/10a (9) where: v bot = 0.96 + (i load * r dson *k t *8); v rmpeak = d*(v in ? 1.8)/(f sw *0.03*r ramp ); i load = the desired maximum load current; r dson = the nominal r dson of the low-side mosfet; k t = the normalized temperature coefficient for the low-side mosfet (on datasheet graph); d = v out /v in duty cycle; f sw = clock frequency in khz; and r ramp = chosen ramp resistor value in k . after 16 consecutive, pulse-by-pulse, current-limit cycles, the fault latch is set and the regulator shuts down. cycling v cc or en restores operation after a normal soft-start cycle (refer to the auto-restart section) . the over-current protection fault latch is active during the soft-start cycle. use 1% resistor for r ilim . loop compensation the loop is compensated using a feedback network around the error amplifier. figure 23 shows a complete type-3 compensation network. for type-2 compensation, eliminate r3 and c3. figure 23. compensation network since the fan2108 employs summing current-mode architecture, type-2 compensation can be used for many applications. for applications that require wide loop bandwidth and/or use very low-esr output capacitors, type-3 compensation may be required. protection + _ v cc 1 0a ilimit ilim rilim + _ ilimit adjust max + _ comp pwm verr pwm ilimtrip vilim ramp
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan2108 ? rev. 1.0.2 12 fan2108 ? tinybuck?, 3-24 v input, 8 a, high-efficiency , integrated synchronous buck regulator the converter output is monitored and protected against extreme overload, short-circuit, over-voltage, under- voltage, and over-temperature conditions. an internal fault latch is set for any fault intended to shut down the ic. when the fault latch is set, the ic discharges v out by enhancing the low-side mosfet until fb<0.25 v. the mosfet is not turned on again unless fb>0.5 v. this behavior discharges the output without causing undershoot (negative output voltage). under-voltage shutdown if voltage on the fb pin remains below the under-voltage threshold for 16 consecutive clock cycles, the fault latch is set and the converter shuts down. this protection is not active until the internal ss ramp reaches 1.0 v during soft-start. over-voltage protection / shutdown if voltage on the fb pin exceeds the over-voltage threshold for two consecutive clock cycles, the fault latch is set and shutdown occurs. a shorted high-side mosfet condition is detected when sw voltage exceeds ~0.7 v while the low-side mosfet is fully enhanced. the fault latch is set immediately upon detection. the two fault protection circuits above are active all the time, including during soft-start. auto-restart after a fault, en pin is discharged by a 1 a current sink to a 1.1 v threshold before the internal 800 k pull-up is restored. a new soft-start cycle begins when en charges above 1.35 v. depending on the external circuit, the fan2108 can be configured to remain latched-off or to automatically restart after a fault. table 1. fault / restart configurations en pin controller / restart state pull to gnd off (disabled) pull-up to v cc with 100k no restart ? latched off(after v cc comes up) open immediate restart after fault cap. to gnd new soft-start cycle after: t delay (ms)=3.9 ? c(nf) with en is left open, restart is immediate. if auto-restart is not desired, tie the en pin to the vcc pin or pull it high after v cc comes up with a logic gate to keep the 1 a current sink from discharging en to 1.1 v. figure 24 shows one method to pull up en to v cc for a latch configuration. 14 fan2108 15 100k en vcc 3.3n figure 24. enable control with latch option over-temperature protection (otp) the chip incorporates an over-temperature protection circuit that sets the fault latch when a die temperature of about 150c is reached. the ic restarts when the die temperature falls below 125c. power-good (pgood) signal pgood is an open-drain output that asserts low when v out is out of regulation, as measured at the fb pin. thresholds are specified in t he electrical specifications section. pgood does not a ssert high until the fault latch is enabled (t1.0). pcb layout figure 25. recommended pcb layout
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan2108 ? rev. 1.0.2 13 fan2108 ? tinybuck?, 3-24 v input, 8 a, high-efficiency , integrated synchronous buck regulator physical dimensions a) dimensions are in millimeters. b) dimensions and tolerances per asme y14.5m, 1994 top view bottom view recommended land pattern 2x 2x side view seating plane c) dimensions do not include mold flash or burrs. f) drawing filename: mkt-mlp25arev3 d) design based on jedec mo-220 variation wjhc all values typical except where noted e) terminals are symmetrical around the x & y axis except where depopulated. optional lead design (leads# 1, 24 & 25 only) scale: 1.5x figure 26. 5x6 mm molded leadless package (mlp) package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan2108 ? rev. 1.0.2 14 fan2108 ? tinybuck?, 3-24 v input, 8 a, high-efficiency , integrated synchronous buck regulator

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